DDR RAM stands for Double Data Rate Random Access Memory. DDR2 is the second generation of DDR RAM. DDR and DDR2 are both types of SDRAM. The key difference between DDR and DDR2 is that in DDR2 the bus is clocked at twice the speed of the memory cells, so four words of data can be transferred per memory cell cycle. Thus, without speeding up the memory cells themselves, DDR2 can effectively operate at twice the bus speed of DDR.

Comparison chart

DDR versus DDR2 comparison chart
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Voltage 2.5 Volts (standard); 1.8 V (low voltage) 1.8 Volts (standard); 1.9 V (high performance)
Speed 200 MHz, 266 MHz, 333 MHz, 400 MHz 400 MHz, 533 MHz, 667 MHz, 800 MHz, 1066MT/s
Modules 184-pin DIMM unbuffered registered; 200-pin SODIMM; 172-pin MicroDIMM 240-pin DIMM unbuffered registered; 200-pin SODIMM; 214-pin MicroDIMM
Prefetch Buffer 2n 4n
Release year 2000 2003
Data Strobes Single-ended Single-ended or differential
Chipset support All DTs, NBs, and servers All DTs, NBs, and servers
Bus clock 100-200 MHz 200-533 MHz
Succeeded by DDR2 DDR3
Internal Rate 100-200 MHz 100-266 MHz
Package TSOP (66 pins) (Thin Small Outline Package) FBGA only (Fine Ball Grid Array)
Transfer Rate 0.20-0.40 GT/s (gigatransfers per second) 0.40-1.06 GT/s (gigatransfers per second)
Read Latency 2, 2.5, 3 Clock cycles 3 - 9 clock cycles, depending upon settings
Channel Bandwidth 1.60-3.20 GBps 3.20-8.50 GBps
Write Latency 1 clock cycle Read latency minus 1 clock cycle
Internal banks 4 4 or 8

Speed of DDR vs DDR2 RAM

DDR2's bus frequency is boosted by electrical interface improvements, on-die termination, prefetch buffers and off-chip drivers. However, latency is greatly increased as a trade-off. While DDR SDRAM has typical read latencies of between 2 and 3 bus cycles, DDR2 may have read latencies between 4 and 6 cycles. Thus, DDR2 memory must be operated at twice the bus speed to achieve the same latency in nanoseconds.

On-Die Termination

With DDR, excess signal noise was eliminated by resistors built into the motherboard, but DDR2 has the terminating resistors built into each memory chip. On-Die Termination for both memory and controller in DDR2 improves signaling and reduces system cost.


Another cost of the increased speed is the requirement that the chips are packaged in a more expensive and more difficult to assemble BGA package as compared to the TSSOP package of the previous memory generations such as DDR. This packaging change was necessary to maintain signal integrity at higher speeds.

Power Savings with DDR2

Power savings are achieved primarily due to an improved manufacturing process through die shrinkage, resulting in a drop in voltage requirements (1.8 V compared to DDR's 2.5 V). The lower memory clock frequency may also enable power reductions in applications that do not require the highest available speed.

History and Launch of DDR and DDR2

DDR2 was introduced in the second quarter of 2003 at two initial speeds: 200 MHz (referred to as PC2-3200) and 266 MHz (PC2-4200). Both performed worse than the original DDR specification due to higher latency, which made total access times longer. However, the original DDR technology normally tops out at speeds around 266 MHz (533 MHz effective). DDR2 started to become competitive with the older DDR standard by the end of 2004, as modules with lower latencies became available.

DDR2 was succeeded by DDR3, which offers faster bus speeds and peak throughput, and a maximum memory of 16GB. For more details, see DDR2 vs DDR3.

Schematic of the physical design of DDR2, DDR3 and DDR4 DIMMs.
Schematic of the physical design of DDR2, DDR3 and DDR4 DIMMs.

Compatibility of DDR2 with DDR

DDR2 DIMMs are not designed to be backwards compatible with DDR DIMMs. The notch on DDR2 DIMMs is in a different position than DDR DIMMs, and the pin density is slightly higher than DDR DIMMs. DDR2 is a 240-pin module, DDR is a 184-pin module.

Faster DDR2 DIMMs though, are compatible with slower DDR2 DIMMs. The memory would just run at the slower speed. Using slower DDR2 memory in a system capable of higher speeds results in the bus running at the speed of the slowest memory in use.


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